1. Field of the invention
This invention relates generally to a semiconductor integrated circuit fabrication method and, more particularly to a semiconductor integrated circuit fabrication method by which a semiconductor integrated circuit with a high degree of integration almost equal to that of a semiconductor integrated circuit fabricated by using a manual design method can be designed, and with a design time and design labor by a designer equal to those required for a semiconductor integrated circuit obtained by using a standard cell design method.
2. Description of the Prior Art
Conventionally, there are three methods for the design of large scale integrated (LSI) circuits. The first method is called a full-custom design method in which transistors and other circuit elements are designed on a semiconductor substrate for every LSI design. By this method a physical mask layout with a very small area can be designed for a LSI with a high performance. However, with this design method much time is required to design the LSI. This is a problem.
The second design method is called a gate array design method in which many transistor elements and the like are preliminarily formed in a matrix on a semiconductor substrate as a wafer. In this case, various block functions have already been designed and registered in a library as basic cells each having a predetermined configuration. A designer combines the basic cells and designs only the wiring among the basic cells while referring to the basic cells in the library, then exposes the basic cells on the actual wafer through a mask to obtain a required chip. By using the gate array design method, a designer can design an LSI having a required function in a short time.
The third design method is called a standard cell design method, and is midway between the full-custom design method and the gate array design method in design time and cost. In this case, an optimum arrangement of elements such as transistors and wiring has already been determined in a cell. A designer combines cells to obtain a LSI with a required function while referring to the cells stored in a library. A designer can design an LSI using the standard cell method faster than by the full-custom method. However, in this case, a wafer for each LSI must be formed because the cell arrangement on a semiconductor substrate is different for each LSI design. The standard cell method takes much time as compared to the gate array method. However, the standard cell method is commonly used as the most simple and convenient method.
Recently, a combination of the three design methods described above has been widely used for design of a LSI. For example, one part of a chip is designed using the full-custom design method, and another part in the same chip using the standard cell design method. This combination design method can be used to efficiently design an LSI.
Generally, a pattern in a cell cannot be changed when the cell is arranged and wired to other cells in the standard cell design method. Therefore when many cells are arranged to form a circuit having a required function, the same pattern is formed between adjacent cells. On the other hand, when the full-custom design method is used, the pattern between adjacent cell is not the same. This way, the degree of integration in a chip can be decreased when the standard cell design method is applied to a design for a LSI because there are many dead areas in the chip.
In addition, the conventional standard cells are designed with the idea that only standard cells are arranged on a chip. For example, the load of a standard cell is changed by the amount of fan-in or fan-out. However, in general, the dimensions of an output driver for each standard cell are designed larger because various combinations of the standard cells are used for an LSI design. The gate length for each transistor in a LSI designed by the standard cell design method is large. However, a designer can easily design an LSI by using the standard cell design method.
For example, one half portion of a chip is designed by the standard cell design method. A maximum total wiring length among the standard cells in the half portion is the same as half of the total wiring length obtained when all chips are designed by the standard cell design method. In addition, the load on the half portion is the same as half the total load of the chip. In this case, the quality of the standard cells in the half portion exceeds the required quality level. These standard cells have over quality. This problem is also caused when the standard cells are used in different sized chips.